In computing, a bus is defined as a set of physical connections (for example, cables, printed circuits, etc.) that can be shared by multiple hardware components in order to communicate with one another. The purpose of buses is <boldWto reduce the number of pathways needed for communication</bold> between the components, by carrying out all communications over a single data channel. This is why the metaphor of a data highway is sometimes used.
If only two hardware components communicate over the line, it is called a hardware port, (such as a port or parallel port).
There are different types of computer buses. A bus is characterized by the amount of information that can be transmitted at once. This amount, expressed in bits, corresponds to the number of physical lines over which data is sent simultaneously. A 32-wire ribbon cable can transmit 32 bits in parallel. The term width is used to refer to the number of bits that a bus can transmit at once.
Additionally, the bus speed is defined by its frequency (expressed in Hertz), the number of data packets sent or received per second. Each time that data is sent or received is called a cycle.
It is possible to find the maximum transfer speed of the bus, or the amount of data that it can transport per unit of time, by multiplying its width by its frequency. For example, a bus with a width of 16 bits and a frequency of 133 MHz has a transfer speed equal to:
16 * 133.106 = 2128*106 bit/s,
or 2128*106/8 = 266*106 bytes/s
or 266*106 /1000 = 266*103 KB/s
or 259.7*103 /1000 = 266 MB/s
In reality, each bus is generally constituted of 50 to 100 distinct physical lines, divided into three subassemblies:
There are generally two buses within a computer.
What is “chipset”? A chipset is the component that routes data between the computer's buses, so that all the components that make up the computer can communicate with each other. The chipset originally was made up of a large number of electronic chips, hence the name.
It generally has two components. The first is the NorthBridge (also called the memory controller) that is in charge of controlling transfers between the processor and the RAM; this is the reason why it is located physically near the processor. It is sometimes called the GMCH, for Graphic and Memory Controller Hub.
The second is the SouthBridge (also called the input/output controller or expansion controller) that handles communications between peripheral devices. It is also called the ICH (I/O Controller Hub). The term bridge is generally used to designate a component that connects two buses:
It is noteworthy that, in order to communicate, two buses must have the same width. This explains why RAM modules sometimes have to be installed in pairs (for example, early Pentium chips, whose processor buses were 64-bit, required two memory modules each 32 bits wide).
Here is a table that gives the specifications for the most commonly used buses:
|Standard||Bus width (bits)||Bus speed (MHz)||Bandwidth (MB/sec)|
|PCI 64-bit 2.1||64||66||508.6|
|AGP (x2 Mode)||32||66x2||528|
|AGP (x4 Mode)||32||66x4||1056|
|AGP (x8 Mode)||32||66x8||2112|
|Serial ATA (S-ATA)||1||180|
|Serial ATA II (S-ATA2)||2||380|
|SCSI-2 - Fast||8||10||10|
|SCSI-2 - Wide||16||10||20|
|SCSI-2 - Fast Wide 32 bits||32||10||40|
|SCSI-3 - Ultra||8||20||20|
|SCSI-3 - Ultra Wide||16||20||40|
|SCSI-3 - Ultra 2||8||40||40|
|SCSI-3 - Ultra 2 Wide||16||40||80|
|SCSI-3 - Ultra 160 (Ultra 3)||16||80||160|
|SCSI-3 - Ultra 320 (Ultra 4)||16||80 DDR||320|
|SCSI-3 - Ultra 640 (Ultra 5)||16||80 QDR||640|